1. Field of the Invention
The present invention relates to a substrate for a display and, particularly, to a substrate for a liquid crystal display having thin film transistors (hereinafter referred to as “TFTs”) as switching elements which can be easily repaired for defects such as breakage and inter-layer shorting attributable static electricity generated at manufacturing steps.
2. Description of the Related Art
Active matrix type liquid crystal displays are widely used as flat panel displays having high image quality in electronic apparatus such as computers and wide-screen television sets.
A liquid crystal display has an array substrate, an opposite substrate provided opposite to the array substrate, and a liquid crystal layer sealed between the array substrate and the opposite substrate. The array substrate has a pixel electrode formed at each of a plurality of pixel regions and a TFT connected to each pixel electrode as a switching element. An opposite electrode is formed on an entire surface of the opposite substrate. The liquid crystal display is enabled for display utilizing the liquid crystal by applying a voltage to the liquid crystal layer from the pixel electrodes and the opposite electrode.
FIG. 10 is a schematic view of apart of an array substrate taken on a surface of the substrate. As shown in the same figure, a plurality of gate bus lines 1010 are disposed in parallel with each other on an array substrate 1001, a scan signal for selecting pixel electrodes to be driven being sequentially input to the gate bus lines. A plurality of drain bus lines 1020 to which a gradation signal is input are disposed on the array substrate 1001 substantially orthogonally to the plurality of gate bus lines 1010.
A pixel region is constituted by each of rectangular regions defined in the form of a matrix by the plurality of gate bus lines 1010 and the plurality of drain bus lines 1020 which are orthogonal to each other. A display area (a) is constituted by an array of a plurality of such pixel regions. In each of the pixel regions, there is provided a TFT 1040, a pixel electrode 1030 and a storage capacitor element (or storage capacitor forming sections) 1050 for suppressing fluctuation of the potential at the pixel electrode 1030.
A plurality of storage capacitor bus lines 1060 is disposed on the array substrate 1001. The storage capacitor bus lines are formed in the horizontal direction in the figure in parallel with the gate bus lines 1010 in connection with the plurality of storage capacitor bus lines 1050. A storage capacitor common electrode section 1070, which combines the plurality of storage capacitor bus lines 1060 and serves as a common electrode for them, is disposed on the array substrate 1001 such that they extend in the direction of intersecting the gate bus lines 1010 (lengthwise direction in the figure). The storage capacitor common electrode section 1070 is formed on the gate bus lines 1010 with an insulation film (not shown) interposed between them.
A plurality of connection terminal sections such as TAB terminals are provided along each edge of the array substrate 1001. Predetermined signals are supplied to the gate bus lines 1010 and the drain bus lines 1020 from the connection terminal sections.
The gate bus lines 1010 and the drain bus lines 1020 are basically vulnerable to static electricity because they are formed on a glass substrate having insulating properties. For example, when static electricity generated on the array substrate 1001 flows in through the gate bus lines 1010 at a manufacturing step (in the direction indicated by the arrow E1 in the figure), it is discharged at regions where the gate bus lines 1010 and the storage capacitor common electrode section 1070 overlap each other to cause inter-layer shorting S. Static electricity not only originates from charging that occurs when the substrate is peeled off from a stage during manufacture but also can enter the substrate from the outside.
A gate bus line 1010 having inter-layer shorting S is subjected to the problem of line defects in the extending direction of the bus line, which results in a significant reduction in the yield of manufacture of panels. In particular, static electricity is likely to enter from the connection terminal sections, and static electricity which has entered in such a location can be discharged to a capacitor component that is present in its path to break down the capacitive section. In such a case, repair by using a laser beam must be performed to remove the shorting location S by cutting the gate bus line 1010, and the repair has been virtually impossible.
The trend toward larger liquid crystal displays with higher definition requires, the wiring width of a storage capacitor common electrode section 1070 to be great in order to reduce its resistance. As a result, since the surface area of overlapping regions where gate bus lines 1010 and a storage capacitor common electrode section 1070 overlap, the problem of the breakage of capacitive sections becomes more significant.
Patent Document 1: Japanese Unexamined Published Patent Application No. 2003-156763